Automation of working machines



May 2, 1967 H. B. F. JENSEN AUTOMATION OF WORKING MACHINES 9 Sheets-Sheet 1 Filed Nov. 26, 1962 INVENTUR.

Befrga. N53265:!)

- ATTORNEYS y 2, 1967 H. B. F. JENSEN 3,317,894

AUTOMATION OF WORKING MACHINES Filed Nov. 26, 1962 9 Sheets-Sheet Z cu A INVENTUR. Her-man Gdarga, F kj A TI'ORNE 5 May 2, 1967 H. B. F. JENSEN 3,317,894

AUTOMATION 0F WORKING MACHINES Filed Nov. 26, 1962 9 Sheets-Sheetfi IN VEN TOR. Herman umKI'ensm BY I ATTORNE S y 2, 1967 H. B. F. JENSEN 3,317,894

AUTOMATION 0F WORKING MACHINES Filed Nov. 26, 1962 9 Sheets-Sheet 4 M, w s

INVENTOR. Herman airga BY m aw A TTORNE YS May 2, 1%? H. B. F. JENSEN AUTOMATION OF WORKING MACHINES 9 Sheets-Sheet 5 Filed Nov. 26, 1962 xfi m h w m W H Arromysvs May 2, 1967 H, B. F. JENSEN AUTOMATION OF WORKING MACHINES Filed Nov. 26, 1962 9 Sheets-Sheet 6 z; A TTORNE Y5 Herman Brte. MKJE MH BY y 2, 1967 H. B. F. JENSEN 3,317,894

AUTOMATION OF WORKING MACHINES Filed Nov. 26, 1962 9 Sheets-Sheet 7 GIL Men

rm, rm rm,

J do;

' to M;

INVENNR.

Human w -bfiFunckx @mt g A TTORNE Y5 May 2, 1967 H. a. F. JENSEN AUTOMATION 0F WORKING MACHINES 9 Sheets-Shet 8 Filed Nov. 26, 1962 w Sm Q6 E 5 INVDVTOR. Hexrnn BQw-ga ur-:Xhsu, BY w x ATTORNEY May 2, 1967 9 Sheets-Sheet 9 Filed Nov. 26. 1962 I 33 aims I1 kins INVENTUR. He mar 54 $9. FuncKSQmn A TTORNE S United States Patent 3,317,894 AUTOMATION 0F WORKING MACHINES Herman Bprge Funck Jensen, 16 Moller Meyersvej, Risskov, Denmark Filed Nov. 26, 1962, Ser. No. 239,925 Claims priority, application Great Britain, Dec. 27, 1961, 46,270/ 61 28 Claims. (Cl. 340--147) This is a continuation-in-part of my application Ser. No. 180,159 filed Mar. 16, 1962 as a continuation-impart of my application Ser. No. 689,620 filed Oct. 1, 1957, now abandoned, and relating to automatic control systems.

The present invention relates to automation of working machines.

It is an object of the invention to provide control apparatus for running a working machine automatically through a cycle of operations.

It is a further object of the invention to provide a sequence control for a working machine having a plurality of electrically controlled operation performing members adapted to perform a programme.

Still a further purpose of the invention is to provide control means for use in a control system for running a machine having a plurality of electrically controlled operation performing members controlled by command signals and a plurality of data signal means adapted to pro duce data signals through a cycle following a predetermined sequence.

Still a further purpose of the invention is to provide a machine control including progressively operable electrical control means as a plug-in control for an automation system to be used with a working machine having electrically controlled operation performing members and data signal means as hereabove mentioned for running a machine through a predetermined cycle.

Still a further purpose of the invention is to provide control means for use with a working machine having machine function means controlling a plurality of machine functions and adapted to be actuated by electrical command signals and data signal means operable to produce data signals indicative of the progress of the operation cycle of the machine functions and having a progressively operable switch means operable to provide data logging and to control transmission of the command signals in programmed sequence responding to the data logging.

Still a further purpose of the invention is to provide an automation system for a Working machine for running the machine through a programme by means of electrically controlled operation performing means which include data signal means adapted to produce data signals indicative of the progress of the machine cycle.

Further objects, purposes and advantages of the invention will appear from the following description with reference to the accompanying drawing, in which FIGURE 1 is a schematic perspective illustrationof a control apparatus according to the invention in combination with a working machine having a machine equipment enabling the machine to be run automatically through a cycle of operations by means of the control apparatus,

FIGURE 2 is a schematic diagrammatic illustration of the control apparatus of FIGURE 1,

FIGURE 3 is a more detailed schematic diagrammatic illustration of the circuit arrangement of the apparatus of FIGURE 1 in one embodiment,

FIGURE 4 is a more specific circuit arrangement of an apparatus according to the invention,

FIGURE 5 is a circuit arrangement as shown in FIG- URE 4 illustrating some further details,

FIGURE 6 is a circuit arrangement illustrating connection between two control apparatuses according to the invention,

3,317,894 Patented May 2, 1967 FIGURE 7 is a circuit arrangement illustrating a detail of the arrangement of FIGURE 6,

FIGURE 8 is a modification of the arrangement of FIGURE 6 illustrating another connection between apparatuses according to the invention, and

FIGURE 9 is a general circuit arrangement of an apparatus according to FIGURE 8.

FIGURES 1, 2, and 3 show the outlining of a control system as follows:

In the circuits to be described transistors are used and in explaining the operation of the transistors a closed transistor means a transistor which is switched on and thereby closes the circuit, and an open transistor is one which is turned olf so that the circuit is open.

In FIGURE 1 CU is a control unit which includes a progressive binary counter device. Included in the control unit is an indexing device for switching the binary counter means of data signals produced on the machine during the automatic sequencing so as to eflectively provide data logging.

The control unit CU further includes means operable to control transmission of command signals to the machine function means at predetermined stages of the progressive switch arrangement orwhich is the samenumerical values of the digital counter device.

The working machine A is illustrated in the form of a drilling machine as of FIGURE 6 in my application Ser. No. 180,159 which illustrates a simplification of the drilling machine disclosed in my U.K. Patent No. 878,902, both of which are hereby made part of the present disclosure.

The construction of the machine equipment as well as the lay-out of the automation system may be as described in my application Ser. No. 180,117 filed Mar. 16, 1962 as a continuation-in-part application of my application Ser. No. 689,620, now abandoned, as well as in my U.K. Patent No. 873,903, both of which are hereby also made part of the disclosure of the present application.

More specifically, the drilling machine of FIGURE 1 is provided with a magazine 102 for a stack of workpieces, the lowest of which is located in a feeding channel at the top surface of a table 108 below a cover plate 109. The forward transport and push-out after the drilling operation is effected by means of a reciprocable slide 110 which moves in the rear end of the feeding channel and is controlled by means of a machine function member in the form of a cylinder H In order to clamp the workpiece during the drilling operation a pressure shoe 117 is provided operable to engage the workpiece from the underside through an aperture in the table 108.

The pressure shoe is rendered effective and ineffective by means of an operation performing member in the form of a cylinder H Eventually a third operation performing member in the form of a cylinder H is provided for controlling the up and down movement of the drill.

The movement of the piston in each of the cylinders is controlled by means of pressure fluid from a pipe line (not shown) including solenoid valves adapted to be energized and de-energized so as to thereby control access of fluid to the cylinders. Such hydraulically or pneumatically operable cylinders for automatic controls as well as solenoid valves are available in a plurality of commercial embodiments and will, therefore, not be described in further detail insofar as those skilled in the art are believed to be able to build up a machine equipment with cylinders and solenoids for automatic control of a machine.

Neither the lay-out nor programming of the automatic cycle of the machine which is described in great detail in my co-pending applications and UK. patents referred to hereinabove will be described in any great detail.

The machine equipment further includes, in addition to a starter switch U a plurality of data signal means operable to produce data signals indicative of the progress of the automatic cycle of the machine and exemplified by sensing switches referred to by U U U U In FIGURE 1 the respective sensing switch is as shown diagrammatically only to facilitate the survey of the wiring. The switch U indicates the forward movement of the transport slide 110, the switch U indicates the operation of the clamping shoe 117. The switch U indicates the completed down-stroke of the drill when the drilling has been completed, and the switch U indicates the return of the drill to its inoperative position. The switch U indicates the inoperative position of the clamping shoe 117, and eventually .the switch U7 indicates the return of the transport slide 110 to inoperative position.

The machine equipment further includes a sensing switch U which is kept closed as long as there are workpieces in the magazine, a sensing device adapted to provide a data signal responding to throw-out of the workpiece. This sensing device is in the form of a light source 96 adapted to activate a light-sensitive device 97 to be explained in more detail as follows. In broad terms, the light-sensitive device 97 includes a sensing switch US(9) operable to produce a data signal in response to shadow, namely when the light beam is broken by the workpiece which is thrown out, and a further switch UL(10) adapted to thereafter produce a data signal on correct continuous function of the light source. It will be obvious that, if only a shadow signa was produced and the light source fails, the automatic machine cycle would continue even if no workpiece were thrown out.

The one terminal of all the data signal means or sensing switches is connected to a common line y together with individual lines from the other terminal of each of the sensing switches, the line y terminating in a socket U.

In a similar way one terminal of each of the machine function members or actuator means for the cylinders, such as solenoid valves are connected to a common line x which terminates in a socket H" together with individual lines from the other terminal of each of the machine function members, such as are indicated schematically in FIGURE 2, in which, however, for .the sake of clearness only six of the data signal lines are shown and the machine is schematically referred to by A. V

The control apparatus CU which is shown schematically in FIGURE 2 is provided with corresponding sockets or similar complementary connector means referred to by U and H adapted to be connected with respective of the sockets U" and H" by cable connections.

In the control apparatus the common lead y of the data signal lines is connected to the input of a network to be more fully described in the following and referred to by INP, the output of which through a lead s is connected to the input of the counter device PS. A voltage source W is shown operable to supply the INPnetwork as well as counter device PS with voltage.

As explained in great detail in my co-pending applications and U.K. patents referred to hereinbefore the counter device which operates as a digital counter has a plurality of stages, each of which together with a predetermined one of the sensing switches effectively provides a coincidence means operable to produce a data signal through the line y to thereby switch the counter device and thereby render another one of the coincidence means operable simultaneously with providing data logging in the form of numerical values or digits of the counter device which thereby operates as a memory.

In FIGURE 2 the data signal lines which extend from the progressive switch arrangement PS are referred to by a Mg, a a a and u and the command signal lines are referred to by h h and h In the control apparatus command signal control relays are included referred to by RA, RB and RC which are of the on-olf type which switches from ON to OFF" and vice versa in response to receipt of consecutive signals as explained in great detail in my co-pending applications and U.K. patents referred to hereabove.

In order to distribute the command signals to the command signal control relays and thereby program the sequence, a distributor member M such as in the form of an appropriately wired plug boardis included in the command signal lines operable to connect the central relays with the counter device PS to effectively apply the consecutive signals to the relays so as to thereby cause the initiation and termination of the respective correlated machine function members at the predetermined stages of the counter device.

As is apparent from the foregoing, the operation of the schematic circuit arrangement of FIGURE 2 included in the apparatus CU of FIGURE 1 in combination with the drilling machine is as follows:

The closing of the starter switch U advances the counter device to stage number two. Provided that there are workpieces in the magazine, the sensing switch U will remain closed and advance the counter to stage number three. At this stage the wiring of the distributor member M activates the relay RA which closes its contact and thereby provides a command signal to the transport cylin- (161' H2. 7

Upon forwarding of the workpiece, the closing of the sensing switch U switches the counter to stage number four. During the forward transport of the workpiece, the old workpiece is thrown out and at stage number four the sensing device 97 operates to make sure that the old workpiece has been thrown out. A shadow signal corresponding to closing of the switch US(9) is transmitted to the counter device and advances the latter to stage number five. The beam from the light source 96 thereafter gives a light signal corresponding to operation of switch U (10) which advances the counter device to stage number six.

At that stage the cross connection in the distributor M activates the relay RB which renders the clamp 117 effective. This causes closing of the switch U and thereby advancing of the counter device to stage number seven at which the relay RC is energized and renders the drill control effective to move the drill down. When the drill has been moved down, this closes the switch U which advances the counter to stage number eight. At that stage the second cross connection in the distributor M to the relay RC de-energizes the relay RC, whereby the drill moves up again and closes the switch U This advances the counter to stage number nine in which the second cross connection to the relay R'B de-energizes this relay and renders the clamp 117 ineffective. This closes the switch U whereby the counter is advanced to stage number ten. At this stage the second cross connection to the relay RA renders the transport ineffective and returns the transport slide so as to condition the machine equipment for the repetition of a new cycle of operations in the manner here described, due to the fact that the switch U is closed.

Each of the closings of the sensing switches provides a signal to the INP element which, as will be described more fully in the following, is in the form of a network.

which in the case of a continuous input signal is capable of producing a plurality of regular well-defined indexing or shifting signals for the progressive switch arrangement with predetermined time intervals or in response to a flash input signal is capable of producing only one welldefined indexing signal.

As apparent from the foregoing, the sensing switches U U will produce signals which continue until the respective mechanical movements have been reversed and would therefore, theoretically be able to produce a plurality of indexing signals. Since, however, the INP element is so designed that it can only produce consecutive indexing signals with predetermined time intervals, the counter device will be switched as soon as the interval after the first indexing signal has been produced which causes the selection of the next data signal line and thereby renders the sensing switch in the preceding line ineffective.

The signals produced by the sensing device 97 are in the form of flash signals, and the INP element is so designed that it is capable of producing a single well-defined signal from a flash input signal.

Preferably the I NP element is designed to produce indexing signals of substantially rectangular curve form.

FIGURE 3 shows schematically the binary counting device which has three binary elements BN BN and BN operable to be shifted to provide a plurality of binary digits in combination with the INP network, which switches the binary counter device upon receipt of the data signals, and binary-to-decimal conversion means shown as a decoder matrix D M providing a plurality of sequentially energizable circuit means effectively energized in decimal sequence in response to the switching of the binary counter device, and means being connected with the operation performing members for deriving command signals for the operation performing members from the decimal lines of the decoder.

The binary networks are in the form of flip-flop circuits interconnected as a binary counter.

In FIGURE 3 also the INP network is shown in more detail. The INP network is adapted to produce indexing impulses to the flip-flops in response to receipt of data signals transmitted through the line y with a curve form substantially as indicated in the INP element of FIG- URE 1.

The INP network is so designed that it can only pnoduce shift impulses at predetermined intervals, so as to avoid the effect of signals which might be produced by exterior disturbances.

The I N P network has in its input circuit a condenser C the potential on which is determined by the potential at the point C which again is determined by a value of the voltage divider. As long as no signal is transmitted through the line y, current is drawn through the voltage divider. When a positive potential is applied to the input from the y-line, the potential at the point C becomes more positive, whereby the normally closed transistor TF is opened and the bi-stable transistor arrangement is switched over, so that the transistor TF is closed. Hereby the potential on the collector of the transistor TF will be positive. This is the positive potential which is applied to the flip-flops. The increase of the positive potential at the point C which controls the opening of the transistor TF is determined by the charging of the condenser C The value of the condenser is such that a signal of a certain duration is required in order to switch over the transistor arrangement TF TF The values of the components can be so chosen that the INP network will only produce switch impulses in response to well-defined data signals and will not respond to undesired signals such as harmonics from operation of the data switches or the like.

When the transistor TF is closed, the normally closed transistor TF is opened, whereby the potential on the collector of the latter transistor becomes negative and causes the normally open transistor TF to be closed. This corresponds to a short-circuiting of the condenser C which thereby is discharged through the transistor TF By the discharging of the condenser, the

potential at the point C becomes more negative, because the semi-conductor diode or valve in the vertical branch of the input circuit prevents a maintained positive command signal from the y-line being applied to the point C. Thereby the transistor TF is closed, which causes opening of the transistor TF This again causes closing of the transistor TR; and opening of the transistor TF During these shiftings of the transistors,'a short but sufliciently well-defined control signal has beentransmitted to switch the flip-flops.

Obviously, the operation of the arrangement of FIG- URE 3 is similar to the operation described briefly with reference to FIGURES 1 and 2,

More specifically, the INP network of FIGURE 3 and its mode of operation are as follows:

Each of the valves, hereinafter referred to, comprises a semi-conductor diode.

Through a valve d the common lead y is connected to a point P in a vertical branch comprising in series connection two resistors r and r a valve d and a resistor r The condenser C as well as the emitter-collector portion of the transistor TF is connected across the valve d and the resistor r As will be appreciated by those skilled in the art none of the transistors are connected directly to the voltage source since the correct biasing of the transistors normally requires a resistor in the connection. These resistors as for example the resistor r; in the collector circuit of the transistor TF will not be referred to in further detail, unless they have some other important function in the entire circuit. The base of the transistor TF is connected to a point between the resistors 1' and r while its collector is connected to the base of the transistor TF and its emitter is connected to a point Q between two resistors 1- and r which together with a resistor r form a voltage divider. The collector of the transistor TF is connected through a valve 01 in the form of a diode to the negative battery voltage and through a valve (1 in the form of a diode and a condenser C to the base of the transistor TF and furthermore directly connected to the inputs of the first of the binary networks EN. The emitter and collector 0f the transistor TF are connected across the battery voltage through suitable stabilizing resistors. The collector of TF is furthermore connected to the base portion of the transistor TF through a condenser C The values of the resistors comprising voltage dividers r r r;,, and r r r are so chosen that the voltage on the base of the transistor TF will be more negative than the voltage on the emitter of this transistor so as to keep this transistor closed whereby current will be drawn through the resistor r the transistor TF and a resistor r The voltage divider r r r is furthermore so chosen that the potential on the emitter of the transistor TF will be less negative than the potential on the collector on the transistor TF as determined by the voltage divider r r and since as this last mentioned potential is applied to the base of the transistor TF it will be understood that the transistor TF will hereby remain opened or switched oif. Since the base of the transistor TF is connected through a resistance r to the positive voltage source while its emitter is connected to the point C which is less positive, this transistor will in this condition be opened. The transistor TF on the contrary, has its base portion connected to the negative source through a resistance and its emitter connected to the positive source so that this transistor will be closed whereby the potential on its collector which is transferred to the base of the transistor TF will be determined by the voltage divider constituted by the stabilizing resistors in the emitter collector circuit of the transistor TF When a positive signal is applied from the line y through the valve d to the point P, the potential at this point will be raised so that the current through the resistors r and r will be lowered. Hereby the potential at the point between the resistors r and r will be more positive. The circuit is so designed that the base voltage by this increase will exceed the positive voltage on the emitter of the transistor TF so as to switch off or open this transistor. The potential on the collector of the transistor TF and herewith on the base of the transistor TF will be governed by its connection with the negative battery terminal only and hereby will be decreased sufficiently below the relatively positive potential on the emitter of the transistor TF to close or switch on this transistor. The collector of the transistor TF is connected with the positive battery terminal so that its potential will be increased. As described above this positive potential is applied to the first binary network BN through the connection shown. At the same time the positive signal passes the valve d.,, in the form of a diode and the condenser C so as to render the base of the transistor TF more positive. The circuit is so designed that the increased base potential of the transistor TF will exceed the positive emitter potential of this transistor so as to thereby open the transistor TF By this opening the collector of TR; will be connected to the negative battery terminal and thereby lower its potential. This decrease in the collector potential is transmitted through the capacitor C and applied to the base of the transistor TF so that the base potential here will now be more negative than the corresponding emitter potential at the point C so as to hereby close or switch on the transistor TF The closing of the transistor TF will tend to decrease the voltage at the point C since this point is now connected with the negative battery terminal through the resistor r Due to the condenser C however, the voltage decrease at the point C will be delayed because the condenser at the first instance will be discharged through the resistor r when the transistor TF is closed. After this discharging the voltage at the point C will be lowered even though a positive signal is still applied to the point P from the common lead y, since such a signal cannot pass the diode valve d The decreased voltage at the point C will also result in a voltage decrease at the point between the resistors r andr so that also the base potential of the transistor TF will be decreased. The circuit is so designed that this base voltage will hereafter be more negative than the voltage on the emitter of the transistor TF so as to hereby cause this transistor to be closed with the result that the voltage on the collector of the transistor TF and thereby on the base of the transistor TF is increased to become more positive than the voltage on the emitter of the transistor TF whereby this transistor will be switched off oropened. By this opening the collector voltage on the transistor TF will be decreased so as to discontinue the positive signal to the first of the binary network BN and to simultaneously render the base of the transistor TF more negative so that this latter transistor due to the positive voltage on its emitter will be switched on or closed. The potential on the collector of the transistor TF will hereby be more positive and this voltage increase will be transmitted through the condenser C to the base of the transistor TF and this transistor will hereby be opened again since the base voltage is now more positive than its emitter voltage.

It will be seen that after hereafter the entire circuit is brought back to its initial condition. 1

It will be appreciated that the INP network as here described will be able to respond to a positive data signal from the y-line which is powerful enough to increase the voltage at the point C sufficiently to open the transistor TF Thus it is :possible to design the circuit in V such a manner that a certain minimum input effect from the y-line is necessary to trigger the circuit. This precaution serves the purpose of excluding faulty input signals of minor effect such as induced signals in the data switch circuit. On the other hand it will be seen that when a sufficient signal has been able to increase the base voltage on the transistor TF and thereby open this transistor, the desired function of the network is no longer dependent on the presence of the input signal. This means that V a well-defined triggering signal determined mainly by the time constant of the RC-link C r will be applied to the binary network BN no matter what the duration of the data signals so that he correct shifting of he binary counters will be assured for even a flashlight data signal.

More specifically, the apparatus illustrated in FIGURE 4 comprises a binary counter device having four binary networks BN BN BN and BN each of which is 8 designed as a flip-flop circuit as shown in more detail in FIGURE 5, and connected as a counter.

The binary digit lines 12 b and b 17 etc. are connected to a decoder matrix having a plurality of output lines which form the data signal circuit line u u n The binary digit lines are connected with the horizontal output lines u a a in the manner shown by the dots, the physical equivalence of which in the embodiment illustrated are the networks DP DP DP or any other convenient networks. The connection between the binary digit lines and the output lines u u u is so that the output lines are rendered operative by the matrix in decimal sequence. In other words, in an initial predetermined condition of the hipflops the first output line a is operative. When the flipfiops are shifted one numerical value to provide digital counting, the second output line a is made operative, etc.

The arrangement is so that the triggering or shifting is eflectuated by means of the data signals provided by the data signal members U U U for connecting the common lead y through an input network INP to the input of the flip-flop chain.

As will be understood, the binary counter hereby operates as a digital counter of the data signals, provided the data signal members U U U are activated in synchronism with the sequence in which the lines u u;, a are made operative.

In other words, the arrangement shown comprises a binary counter device having a plurality of digit flip-flops connected as a counter and a decoder matrix having a plurality of output lines connected with said fiip-fiops so as to select or render one of the output lines operative in response to each binary digit. The circuit arrangement furthermore provides for shifting the binary counter only by a data signal member which is included in the selected or effective one of the matrix output lines.

From the foregoing it will be understood that with the dots shown at the matrix, the shifting of the binary counter by the closing of that one of the matrix output lines which is effective at the corresponding binary digit by actuation of the respective data signal member which is included in that line will render effective another one of the matrix output lines, and thereby condition'the binary counter for switching in response to actuation of the data signal member which is included in that line. The arrangement shown also provides for using the matrix output lines to derive command signals for the operation performing members. To this purpose a plu rality of command signal lines h h h are branched off from the matrix output lines and connected with electrical distributor means M which may be in the form of a plug board having a first plurality of terminals connected to the command signal lines, a second plurality of terminals connected to the control relays RA, RB, RC, and adapted to be cross-wired to actuate the relays in predetermined sequence.

As will be understood, the selection of the output lines u a will take place in a sequence depending on the connection in the matrix as illustrated by the dots. It will, therefore, be possible to provide the connect-ions at the dots governed by the sequence of actuation of the data signal members during the predetermined cycle of the working machine so as to provide the digital counting of the data signals by means of appropriate connection of the matrix. In such event it is not necessary to connect the data signal members to the matrix output lines in any predetermined sequence following a predetermined numbering of the matrix out-put lines to correspond to the sequence of actuation of the data signal members during the machine cycle, because the connection in the matrix automatically will select the output lines to be effective in decimal sequence corresponding to the actuation of the data signal members. In many cases, however, it may be convenient to make the programming of the system connecting the matrix so as to obtain decimal sequence of the matrix output lines and number these lines correspondingly. In such even it will be understood that in order to provide the desired binary digital counting of the data signals, the data signal members must be included in the matrix output lines in the sequence in which they are actuated. This can be done either by analysing the machine cycle in connection with the plan ning of the automation in the manner described in my U.K. Patent No. 878,902, or by including another distributor such as a conveniently wired plug board, in the connection between the matrix output lines and the data signal means.

In the following it will be supposed that the matrix connection dots are provided so as to render the matrix output lines a a u effective in the decimal sequence in which they are numbered in FIGURE 4, and that the machine equipment is designed to actuate the data signal members U U U in the corresponding number sequence.

In brief terms the mode of operation of the arrangement shown in FIGURE 4 hereafter is as follows:

-It is supposed that the four flip-flops are reset to an initial position in which the first matrix output line 11 is rendered operative so that a potential is applied to that line. To simplify the explanation, the data signal means are supposed to be switches closed in the sequence illustrated, though it will be understood that within the scope of the invention the switches may be constituted by electronic networks operable to derive a signal from a matrix line which is rendered operative, for example in response to changes of operating conditions of an electronic device, such as a light-sensitive cell which is included in the network.

When the data signal switch U is closed, a signal is transmitted through the common lead y to the input network INP, whereby the binary counter is shifted to render the second matrix output line a effective. This conditions the binary counter for being switched by closing the data signal switch U When this shifting takes place, the line a is rendered effective. In the embodiment shown in FIGURE 4 a cross connection in the plug board M provides for actuation of the relay RA when the matrix output line u is effective. It is supposed that this causes closing of the appertaining relay contact and thereby actuation of the operation performing member H so as to initiate a machine function.

The relays are in the form of electronic networks to be further described in the following.

When the data switch U is closed, the binary counting of the data signals proceeds to render the matrix output line a effective, and when the data signal switch U is closed, the shifting proceeds to render the line 14 effective. When the line a is effective, the cross connection shown in the plug board M actuates the relay RA again which opens the relay contact and terminates the machine function which is performed by the member H The further cross connection shown from line 5 in the plug board actuates the relay RB and closes the relay contact to initiate a machine function controlled by the member H The shifting and counting proceed in the manner here described. When the matrix output line to, is rendered effective, the relay RB is reactuated to open its contact so as to terminate the machine function performed by the member H and when the matrix line a is rendered effective, the relay RC is actuated to initiate the third machine function controlled by the member H which is terminated by reactuation of the relay RC when the matrix line u is rendered effective.

In the embodiment shown in FIGURE 4 only ten matrix lines are used for the machine equipment and that the matrix output line a when rendered effective, provides a reset signal'to the flip-flops through a reset line 2, whereby the flip-flops are reset to render the first matrix output line u effective again so as to repeat the cycle.

10 It will be understood, however, that with four flip-flops sixteen matrix output lines can be provided which with the arrangement indicated can provide a total of fifteen lines available for the machine control. It will further be understood that any additional number of flip-flops can be used, so that with n flip-flops a matrix with n input line pairs from the flip-flops will render availablefor the machine control 2 -1 outputs with the 2 output available for the reset.

The flip-flops can be used as basic building blocks to provide the desired number of 2 -1.

I have found it convenient, however, to design control apparatuses according to the invention in a standard size having a predetermined number of flip-flops, in the following illustrated as an eaxmple four flip-flops as basic building blocks and then, where necessary, provide for the desired additional number of lines for the machine control to combine such units of standard size in one of the manners to be more fully described hereinafter.

The networks DP DP DP broadly referred to hereinbefore representing the physical equivalents of the dots include gate means to be more fully described with reference to FIGURE 5. Each of the networks DP DP has in addition to the output connected with the lines a a a an output connected with a lead m which is connected with one input of a network generally referred to as RFB, and an input connected with a lead 1 which is connected with an output of the RFB network. The RFB network includes a main control relay which is de-energized if more than a predetermined current is drawn through one of the DP networks, for example due to a short-circuiting through a data switch of the working machine. The de-energization of that relay is controlled through the lead 1 in such event. The relay is also de-energized if for example due to defects in the flip-flops or the DP networks the lines a n n are not rendered properly effective, eg in such a manner that a predetermined well defined potential is applied to more than one of the lines. In such event the actuation of the RFB network relay is controlled through the line m which may be referred to as the more-thanone line. It will be understod that a more-than-one situation, i.e. a condition during which more than one control line is made operative, should be avoided, because it would enable more than one data switch to cause the shifting of the binary counter which can give rise to faulty operation of the machine.

The RFB network furthermore has two outputs, one of which is connected to the reset line z, and to which a reset signal is applied when the apparatus is switched on, so as to ensure that the fiip-flops always start at the predetermined reset binary digit. The second R-FB network output is connected through a line b to a point at the INP network which is operative in response to receipt of a signal to prevent the INP network against shifting the flip-flops in response to data signals through the line y, when the RFB network is de-energized in response to actuation of the RFB network from the output line 7 as well as from the input line m As will be understood from the foregoing, the connections through the lines f, m and b provide safety against faulty operation of the working machine due to defects in the data signal switches, which may cause damage to the control apparatus circuit networks by drawing excessive current therethrough, as well as due to defects in the networks which may cause faulty operation of the machine.

As also shown in FIGURE 4 semi conductor diodes, namely valves are inserted in the matrix output lines or data signal lines to prevent disturbing signals being trans-. mitted back to the matrix networks or DP networks, and in a similar manner such valves are inserted in the command signal lines.

Though it would be possible within the scope of the invention to design the DP networks to derive therefrom in addition to the positive potential applied to the output lines u a u a negative potential to be applied to the machine control relays RA, RB, RC so as to alternately energize and de-energize the relays in response to alternately applied positive and negative signals, it has been found that this may complicate the DP networks, and in addition it would require duplication of the leads to the input side of the distributor M It has therefore been found more convenient to design the relay networks to alternately energize and deenergize the relay winding RB in response to positive input signals only.

For this purpose, as shown in FIGURE 4, the terminals of the plug board M which are connected with the relays are duplicated, and the relay winding is included in an electronic network having two inputs I and 1 to operate as a polarized relay in response to positive input signals only.

The circuit arrangement shown with respect to the relay RA includes three transistors RT RT; and RT of which the transistor RT is in series with the relay winding RV. The transistors RT and RT form a bi-stable circuit which is adapted to be switched to the one condition by means of a positive impulse signal applied to the base of the transistor RT from the input I while shifting of the bi-stable circuit to its other condition is steered by the transistor RT which in its turn is controlled by a positive signal applied to its base through the other input point I More specifically the transistors RT and RT are connected in a bi-stable circuit similar to that shown and described in connection with FIGURE 4. At the initial condition the transistor RT will be closed so as to render the base of the transistor RT sufliciently positive to keep this transistor open so that the relay Winding RV will be de-energized. The input I is connected with a voltage divider comprising resistors r r r which is the voltage divider from which the base of the transistor RT is supplied with that relatively negative potential which enables this transistor to remainclosed. When, however,

a positive signal is applied to the input point I this will cause the voltage on the base of the transistor RT to be increased to such a degree that the transistor will be opened with the result that the voltage on its collector and thus on the base of the transistor RT will become negative so that this latter transistor will be closed so as to energize the relay winding RV.

The input 1 is connected to a voltage divider, comrising resistors r' r' r which, as long as no positive signal is applied to the input I serves to renderthe base of the transistor RT; less positive than the emitter of this transistor so as to thereby keep the transistor closed. In this closed condition the potential on the collector of the transistor RT will also be positive but a valve d, and a biasing resistor r prevents this potential from being applied to the base of the transistor RT When a control signal is applied to the input I; this will cause the potential on the base of the transistor RT to be increased so that this transistor will hereby be opened, whereby the potential on the collector of this transistor will be decreased due to the connection with the negative battery terminal by way of the resistor r' This potential decrease is transmitted through the valve d' to the base of the transistor RT where it will be sufiicient to closerthis transistor whereby its collector potential will be increased from the positive battery terminal through the resistance r so as also to increase the potential on the base of the transistor RT This'means that when a positive signal is applied to the input point I the transistor RT will be opened so as to de-energize the relay winding RV. When the current through the relay winding is broken, this will give rise to a self-induced voltage peak in the coil, and for absorbing this voltage peak an RC-link r' C is shunted across the coil so as to act as a spark-extinguisher to protect the transistor RT Condensers (3' and C;., of relatively high capacitance are shunted across the resistors 1",; and r and connect the input lines of the circuit with the negative battery terminal and serves the purpose of absorbing any induced flash signals or alternating currents which are applied to the input lines. By this precaution it is ensured that the relay circuit described will only respond to well-defined control signals of a predetermined minimum duration.

When the transistor RT is opened in response to a positive signal applied to the input I the base of the transistor will be relatively negative to thereby keep the transistor RT in a switched-off condition as described above. The values of the resistors of the voltage dividers are so chosen that as long as a positive signal is applied to the input I a positive signal which simultaneously applied to the input I will not be sufiicient to increase the potential on the base of the transistor RT to enable the opening of this transistor. This means that the input '1 will be dominating so that the relay always will be de-energized it, due to any faulty operation or short-circuiting in the network, or due to other reasons, the two inputs should receive a command signal at the same time.

As mentioned hereinbefore, the INP network is so designed that it can only produce shifting impulses for the flip-flops at predetermined intervals. This means that each binary digit is retained for a predetermined time which should be long enough to secure desired activation of the control relays RA, RB, and RC. It will be understood that if the shifting of the flip-flops were allowed without delay and the machine equipment includes data signal means producing fiash signals in sequence, this might cause so fast a shifting of the control signals that proper activation of the machine control relays would not be ensured. By introducing a delay factor in the INP network for example of the magnitude of .4 millisecond before a new flip-flop shifting is allowed, it is assured that each control signal of such a duration is always available which is sutficient to obtain actuation of the relays.

It is also desirable to select the values of the resistors of the voltage divider at the input of the INP network to produce a potential on the base of the transistor TF which determines the minimum eifect for which the network is allowed to operate. As an example, it has been found that a minimum efiect of the magnitude milliwatts is convenient. V

In FIGURE 5 the binary flip-flop network BN is shown in more detail; The'network includes two transistors TB and TB;.* When the flip-flop is reset by means of a positive potential throughthe line z, the base of 'the' transistor TB becomes positive, whereby this transistor is opened. This results in negative potential on the collector of the transistor TB and accordingly a negative potential on the lefthand binary input line b to the matrix. This negative potential is supplied to the base of the transistor DB whereby this transistor is retained closed so as to cause positive potential on the collector of the transistor TB; and a positive potential on the righthand binary line b The bi-stable circuit is adapted to be switched over by an impulse transmitted from the IN]? network so as to hereby shift the potential on its output line. The output to the next flip-flop circuit is taken from the collector of the transistor TB Though the design of the flip-flop circuit is well known, the network BN will now be described in some further detail.

As will appear from FIGURE 5 the two transistors T8 and 'I B are arranged in a symmetrical circuit with their emitters connected with the positive voltage source through a biasing resistor R and their collectors through corresponding resistors with the negative battery terminal. Furthermore, the collectors are connected through symmetrical resistors R R' and capacitors C C The 13 output from the INP network is connected to a point T between these capacitors. The bases of the transistors are connected to the output lines b b through the RC-links shown. Furthermore, the bases are connected to the positive battery terminal through resistors R R';;.

In the initial condition the transistor TB is closed so as to connect the output line b with the voltage divider consisting of the two resistances R and the collector biasing resistance R.; of which the resistor R.,, has the higher resistance whereby the output line is rendered positive. Through the RC-link mentioned above this positive potential is also applied to the base of the transistor TB so that the potential thereof will be more positive than the potential on the emitter thereof whereby the transistor TB will remain opened. Under this condition the collector of the transistor TB is connected through the biasing resistor R to the negative battery terminal so that the resulting negative potential will be transferred through the other RC-link to the base of the transistor TB thereby to keep this transistor closed as mentioned above. This negative potential is furthermore applied to the output line b With the collector of the transistor TB positive and the collector of the transistor TB negative it will be seen that the two condensers C C will have positive potential on their righthand side and negative potential on their lefthand side. When now a positive impulse is applied to the input point T between the condensers, this will cause no substantial change of the charge of the condenser C since a positive potential is already present at its righthand side; but the condenser C' will be able to be charged, since its potential seen from the point T is negative. This means that the positive impulse is able to pass the condenser C' and the valve V connected between the base of the transistor TB and the condenser G on the other side thereof. Thus the voltage on the base of the transistor "DB will be increased sufliciently to exceed the positive voltage on the emitter thereof which will result in a switching-off or opening of this transistor. Since a steady positive signal cannot be applied to the collector of the transistor TB through the condenser C' this collector will hereby be rendered negative due to its connection through the resistor R' to the negative battery terminal, and also the output line b will be rendered negative. Through the aforementioned RC-link this negative voltage will also be applied to the base of the transistor TB so as to close or switch on this transistor. Its collector will now be connected to the positive battery terminal through the relatively small resistor R so that the collector as well as the output line b will now become positive.

If a negative impulse had been applied to the point T this would be able to pass the condenser C but it could not pass the valve V so that it would be unable to change the potential of the base of the transistor TB This means that no negative impulse signal to the flip-flop circuit is able to trigger this circuit, i.e. to shift the potential on the output lines thereof.

When a positive signal is applied from the line z through the input of valve V to the base of the transistor TB it will be seen that if this base already is positive, i.e. in the initial condition of the circuit, this will cause no changes in the condition. If, however, the base of the transistor "BB is negative, i.e. in the condition where the output line 11 is negative and b is positive, the positive potential applied to the base of the transistor will shift the condition and thereby shift the entire circuit into its initial condition. It will be understood, therefore, that a positive signal applied through the line z to all the flip-flop circuits will ensure that all these circuits thereafter will be in their initial condition.

Since shifting of the flip-flop networks only takes place in response to positive impulses, the shifting of the first flip-flop network BN in the manner hereinbefore described does not cause any shifting of the next flip-flop network BN Using the code one for negative output from the 14 flip-flops and zero for positive flip-flop output, it will be understood that the first impulse causes a shifting of the binary code from 1111 to 0111, and that the shifting thereafter takes place and provides the binary codes 1011, 0011, 1101, 0101, etc. as indicated in FIGURE 4.

It will be appreciated that the embodiment of the flipflop circuit shown in FIGURE 5 is only an example and that the flip-flop can be designed in a plurality of different ways, and that it is also possible within the scope of the invention instead of transistors to use tunnel diodes in the flip-flop circuits.

In order to render the matrix output lines effective in decimal code sequence, suitable connections are established between the binary digit lines and the matrix output lines.

Though it is possible within the scope of the invention to render the matrix output lines effective by means of thermionic or crystal diodes, indicated by the dots shown in FIGURES 4 and 5, in view of the safety precautions the lines and m use is made of the DP networks, one of which DP is shown in more detail in FIGURE 2. The DP network is defining a polarity conversion circuit with a logic type AND gate in the input which requires positive potential on all of the input lines for passing signals.

In order to pass signals through the DP network and thereby to render the first output line U operative to condition the counter for switching in response to closing of the data switch U the four binary digit lines b 11 b and 6 which have positive potential when the binary code is 1111, i.e., when the flip-flops are reset, are connected to the base of a first transistor TD in the network DP through four resistors which define the AND gate.

The network is so designed that the transistor TD is closed as long as at least one of the four input lines shown is negative. The base of the transistor TD is connected to the positive battery terminal through a resistor rd so that the transistor base will be positive as long as positive voltage only or even no voltage at all is applied to the base through the said gate. On the other hand the circuit is so designed that when the base receives negative voltage from only one of the four input lines, this will be sufiicient to decrease the positive base potential relatively to the emitter potential sufficiently to cause the transistor to be closed. With the transistor TD closed the potential on the base of the transistor TD; will be determined by the voltage divider comprising the collector resistor rd in series with the emitter resistor mil and which is shunted by the resistors rd rd This voltage divider is so designed that the potential on the base of the transistor TD will thereby be sutficiently positive relatively to the emitter potential to keep the transistor TD open on the emitter of the transistor TD a positive potential is applied from the RFD network through the line 1 and as it will be appreciated that the data line u will be disconnected from the positive battery terminal which is represented by the line 1 as long as the transistor TD is switched oif or open.

With the binary code 1111, positive potential is applied through all four of the input resistors to the base of transistor TD; whereby the transistor will be opened. Thus the potential on the base of the transistor TD will only be determined by resistors rd rd;; and M1,; comprising the voltage divider and since now the shunt connection through the resistor rd is broken, the base potential of the transistor TD be decreased below the emitter potential so that this transistor will be closed on and made conductive to conect the data line u with the positive voltage supplied through the line 1 whereby the data signal line u with the data switch U as well as the control signal line h will be rendered operative so as to condition the binary counters to be shifted one step when the data switch U is closed.

As far as the first network DP is concerned its transis- 15 tor TD will be closed when the binary counter has the code 1111 because only then is the gate RD operable to open the transistor TD When in response to closing of the data switch U the flip-flops are shifted, the binary code is shifted to -1-1-1. This means that the potential on the output line b is reversed and becomes negative. The gate RD will only receive positive potential through three of its input lines and negative potential through the fourth line which as described above is sufficient to decrease the potential on the base of the transistor TD to such an extent that this transistor will be closed so as to cause the transistor TD to open and thereby to disconnect the positive potential from the signal switch line a and render it inoperative.

The network DP which is designed in a similar way as the network DP has, however, its gate connected with b by, b and by. This connection fulfills the requirement for opening the transistor TD and closing the transistor TD of the DP network through its gate and thereby apply positive potential to the line u to render it effective.

In a corresponding manner the shifting of the binary codes and the corresponding connection of the DP networks, as illustrated in FIGURES 4 and 5, makes the lines u M 11 effective in sequence.

The binary code which corresponds to line No. 11 is 1010, and from the line a the potential is applied directly back to the reset terminals of all four binary flip-flops through the line z in which preferably a suitable amplifier, referred to in FIGURE 4 by zf, is provided operating with a convenient time constant so as to secure proper reset of the binary flip-flops.

As shown in FIGURE 5 the collector of the transistor TD in the DP network is connected through a resistance in series with a valve formed by diode v to an output terminal which is connected to the m line, while the emitter of the transistor is connected to the f-line as described hereinbefore.

The RFB network, which controls the energization and de-energization of the circuits of the control unit, is shown in more detail in FIGURE 5.

The RF-B network is the main control network of the control unit and controls the switching on of the unit by push button control of a starter switch SS SS and delivers, when switched on, a reset-to-zero signal to the binary counters. The RFB network also operates as a circuit breaker, and when switched oif it cuts off the voltage supply through the f-line to the DP circuits of the data signal lines and simultaneously applies an inhibition signal to the shift impulse circuit INP.

The circuit breaking can be activated by means of an emergency switch ESor automatically if excess current is drawn to the data lines through the f-line due to some fault, e.g., earthing of a data switch on the machine or if more than onedata line becomes effective, e.g., due to fault in a DP network.

The starter switch of the RFB network only serves the purpose of switching the unit on and conditioning it for controlling the cycle of operations by setting the binary counter at zero and thereby rendering the first line u effective.

The start of the cycle is, however, dependent'on the closing of the switch U which can be considered as the cycle starter switch on the machine but seen from another aspect also can be considered as a manually operable data or sensing switch which when kept closed provides a data signal for permission to repeat the program automatically in the same manner as the magazine sensing switch as long as it is closed also provides a data signal to the effect that there are workpieces in the magazine and that therefor the cycle can be repeated.

The functions of the RFB network are performed by means of transistor circuits. A.main relay RF is kept energized in a circuit through a transistor FT the closing of which is controlled by means of a transistor FT of a bi-stable transistor arrangement FT FT of which the transistor FT which is kept open during normal switchedon operation is closed by means of a short impulse when the battery is switched on and thereafter opened when the transistor FT is closed in response to actuation of the switch SS In a similar manner as the transistor FT provides a signal to open the relay transistor FT a transistor FT of a bi-stable arrangement FT FT is closed when the battery is switched on and provides the reset-to-zero signal to the binary counter, and is opened when the transistor FT is closed in response to closing of the switch SS so as to thereby remove the reset signal.

The potential to the ;f-line is supplied from a voltage divider in the RFB network which when the current drawn through the f-line is below a predetermined value produces a voltage drop which keeps an auxiliary transistor FT open which in its turn is connected with the bistable arrangement FT FT to reverse the condition of this arrangement when it is closed which it will be due to change of the above-mentioned voltage drop when excess current is drawn through the f-line. Obviously this closes the transistor FT and thereby de-energizes the relay. The bi-stable arrangement has also a point of its voltage divider circuit connected with the m -line in such a manner that the bi-stable arrangement is reversed from the condition with FT open and FT- closed if more than one data line is effective so as to thereby de-energize the relay.

Eventually the relay circuit can be broken by manual action by operating an emergency switch ES. In such event a circuit branch provides an impulse to reverse the condition of the bi-stable arrangement FT FT As it will be appreciated it will in all the cases when the relay is de-energized be combined with a reversing of the FT FT arrangement which will require manual operation of the starter switch for restarting.

More specifically, the relay RF has its relay winding in series with the transistor FT a biasing resistor rt the manually operable start switch portion SS and the normally closed emergency switch ES. The start switch portion SS is mechanically connected with the second start switch portion SS which through equal circuit branches including resistors rt and rt valves dt and dt and capacitors C and C is connected with the base of each of two transistors -FT and FT so that when the switch SS is closed ashort negative impulse will be applied to: both these transistors whereby both of them will be closed whenthe'control unit is switched on. When the battery is switched on a short negative voltage impulse will be applied to the base of the transistor FT through an RC-link comprising a resistor H and a condenser ct This impulse, the duration of which is determined by the time constant of the RC-link, will be sufiicient to render the transistor FT closed or conductive for so long a time that the positive voltage on its collector which is supplied to the binary counter through the reset z can reset all of the binary elements to zero.

The reset signal through the line z must be removed and to this purpose the base of the transistor FT receives a negative impulse through another RC-link r1 ct whereby it is closed when the switch SS is closed with the result that the positive 'voltage on its collector will be transmitted through the resistance rt to the base of the transistor FT and thereby open this transistor. A negative potential maintained on the base of the transistor FT through the voltage divider resistor rt serves to stabilize this transistor in closed condition which also stabilizes the open condition of the transistor FT so that no reset signal can be applied through the line z during the normal operation of the networks.

The bi-stable transistor circuit FT FT is designed in a similar manner, i.e., with a cross base collector conection for the mutual stabilization of both conditions of the circuit. Initially when the battery is switched on the transistor FT will be closed and produce a negative potential at the point T which will close the transistor FT and thereby condition the relay for actuation when the switch SS is closed.

When the switch SS is actuated, the base of the transistor FT will receive a negative impulse through the RC-link CE, vt as descirbed in connection with the transistor FT whereby the transistor FT will be closed and thereby open transistor FT During normal operation the voltage on the base of the transistor FT will be determined by a voltage divider with resistances ri r1 rt of which the resistance rt is shunted by a series connection of a transistor FT the resistance rt which later will be operative as a shunt to the resistance rt when the transistor FT is closed on, and thereby cause an increase of the potential on the base of the transistor FT In addition the base potential on the transistor FT will vary with the potential on the line m which is connected directly to the base of the transistor FT The potential on the base of the transistor FT is determined by the voltage across the resistance ri The relay RF has an upper contact k which isclosed when the relay is energized and connects the line with the positive voltage source through a suitable resistor rz a lower contact k which when closed provides a self-holding circuit for the relay winding, and a lower contact k which is open when the relay is energized and closes when de-energized and the function of which will be described below. The relay winding RF and the transistor FT are shunted by a resistance H of considerable higher resistance than the relay winding itself.

When the switch SS is closed and the switch BS is in its normally closed position, the relay winding will be energized through the transistor FT which became closed when the transistor FT became closed when the battery was switched on. Since the point T is also connected with the base of the transistor FT the potential at the point T is relatively negative also when the transistor FT is open. As soon as the closing contact k is closed, the relay will be self-holding so that the press button switch SS may be released again. When the contact k is closed, positive potential is derived through the resistor rt the contact k and applied to the line from where it is sequentially applied to the data lines u as described hereinbefore.

From the foregoing description it will be understood that during normal operation there will always be one, but not more than one effective data line. Under such conditions a predetermined current is drawn through the line 1 and through the output transistor TD in the selected one of the DT networks when the data switch in this line is closed. Therefore, it is possible to adjust the two resistors rt rt in such a manner that the normal current in the line produces a voltage drop across the resistance rt which is just enough to keep the transistor FT in an open condition while an increase of this current will decrease the potential on the base of the transistor FT and close this transistor. However, during normal operation the transistor FT will be open with the result that the transistor FT is closed and the transistor F1} is open so as to keep the transistor FT closed as described above.

While the above described arrangement serves to control the current through the line 1, i.e. the input current to the output transistors of the DP network, provisions are also made to control the output current from these transistors. To this end the collector of the transistor TD is connected through a resistance rd and a valve v in the form of a diode to the line m which is connected to the base of the transistor FT The circuits are so designed that an increase in the potential on the line m will open the transistor FT close the transistor FT and thereby open the transistor FT The emergency switch ES may be operated in case of emergency to render the entire circuit inoperative. If this switch is actuated to be opened, the holding circuit for the relay winding RF will be broken, whereby the relay is de-energized and closes the lowest of its contacts k Hereby a negative voltage impulse will be drawn from the negative voltage source through the resistor m the resistor rt the contact k;,, the oppositely directed valve dt and a RC-Iink, rt on; to the base of the transistor FT so that this will become momentarily negative to thereby be closed so as to reverse the condition of the bi-stable arrangement FT FT and to also render the base of the transistor FT positive whereby this transistor will be opened and unable to be closed again as long as the transistor FT is closed unless the starting switch SS SS is again actuated.

When the relay RF is de-energized, the positive potential on the line 1 disappears whereby the operative data line is rendered inelfective and in addition the INP network is inhibited as will be described below.

During fault-free sequencing only one of the DP networks is connected to the four positive output lines from the binary counter at each stage and all the other DP networks are connected to at least one negative binary digit output which is sufficient to render the DP network inoperative. If there is a faulty connection between the DP network and the binary counters, for example due to cold soldering or a defective resistor in one of the gates, the DP network in question will, during the sequence have its three intact inputs connected to positive digit lines. Since the fourth input through which the negative voltage to the base of the input transistor TD is defective the network is not inhibited and it will out of sequence render its data line u operative while at the same time the data line a from the correctly selected DP network is also rendered operative. This would have the effect that not only the wrong u-line, but therewith also a wrong h-line would be rendered effective which might result in actuation of a wrong machine function, out of programmed sequence.

In such an event, the correctly selected DP network as well as the faultily selected DP network will have its output transistor connected with the line m and the resistance rd will hereby be super-imposed by the same normal current from the faulty selected output transistor whereby the total current in the line m will be increased so as to raise the potential on the base of the transistor FT sufficiently to open this transistor which will close the transistor FT to and open the transistor FT to be switched off and thereby de-energize the relay RF.

If, due to a direct short-circuiting in the data signal circuit, more than a predetermined current is drawn through the line f, this will result in an increased voltage across the resistor ri in the RFB network whereby the potential on the base of the transistor FT will be decreased sufiiciently to cause this transistor to be closed whereby as previously explained, the transistor FT is opened, the

transistor F'I is closed, the transistor FT is opened and the relay RF is de-energized.

It will be appreciated that the transistor FIE; in all cases of faulty operation or in response to activation of the emergency switch ES will be opened whereby the potential on the collector of the transistor FT will be rendered negative. The inhibition line b which is connected with the point C in the INP network hereby causes current to be drawn from the point C through the inhibition line b to the negative potential on the collector of the transistor FT whereby the current in the INP network which otherwise would cause a charging of the condenser C is drawn to the RFB network, whereby the charging of the condenser is inhibited. The INP network which is thus rendered insensitive to input signals from the y-line. It will be understood that in order to obtain this action, the time constant of the networks which may be included in the f-line and the l7'll -ll11 to control the RFB network, must be less than the time constant of the INP network.

Preferably a suitable driver network (not shown) is included in the m -line operable to provide a well-defined input as well as to operate with a convenient time constant.

It will be understood that it is also possible within the scope of the invention to provide other reset connections, for example from the distributor'plug board M FIGURE 6 illustrates a series connection between two binary counters each having four flip-flops and a matrix including DP networks as illustrated in FIGURES 4 and 5.

The upper four flip-flops have sixteen matrix output lines of which fifteen are connected to the machine. The sixteenth is used to switch the lower counter on which also has fifteen matrix output lines available for the machine, the sixteenth being used to switch back to the upper flip-flops.

The DP networks in the matrix lines of both counters are connected with a common RFB network from which also reset line z and inhibition line b lead to both counters.

To this purpose a network, generally referred to as MeO, is provided operating as a switch as illustrated schematically in FIGURE 6, with its movable finger connected to the y-line for both flip-flop systems. This movable switch finger can be tripped to alternately connect the y-line with either of two input networks INP and INP for each of the two flip-flop systems.

The reset connections from the z-line are in the lower four flip-flops connected with the upper four flip-flops, so that the reset signal resets the upper flip-flops to zero corresponding to decimal code 1111 which renders the first of the upper matrix lines effective, and with the lower flip-flops so that the reset position renders the sixteenth line effective, i.e. to the last of the matrix line which is not outgoing.

The decimal "line number sixteen of the lower flip-flop system referred to as dc" is operatively connected to the MeO network to shift it as indicated by the arrow to the position shown in full lines. In a corresponding manner the sixteenth decimal line of the upper flip-flop system referred to as dc' is operatively connected to the MeO network to shift it, as indicated by the arrow, to the position shown in dotted lines.

As will be appreciated, this causes the first fifteen decimal lines to be controlled from the upper flip-flop system. When the upper flip-flop system activates decimal line number sixteen, the M60 network is activated to be shifted in the direction of the arrow connected with the line d6 i.e. from the position shown in full lines to the position shown in dotted lines. Since, however, as described hereabove the reset causes the lower flip-flop system to assume a binary code corresponding to decimal number sixteen, means is also provided to shift the lower flip-flop system from decimal number sixteen to decimal number one simultaneously with shifting of the MeO network. This is obtained by means of an impulse network 1N between the line dc and the input network lN P of the lower flipflop system. This network may for example be in the form of a condenser.

During the fifteen sequential selections of the lower fifteen data signal lines controlled by the lower flip-flop system, the upper flip flop system remains in the decimal coded condition corresponding to activation of the line de When, however, the signal fro-m the DP' network of the lower fiip fiop causes a signal through the line dc" to switch the MeO network back to the position shown in full lines, this must also cause a shifting of the upper flip-fiop system. This is caused by means of a second impulse network 1N which provides a signal from the line dc" to the input of the upper flip-flop system IN-P Also this network may be in the form of a condenser.

The MeO network is shown in more detail in FIGURE 7. The input from the line dc of the upper flip-flop system is applied to the base of a transistor MeT and the input from the line dc" of the lower flip-flop system is applied to the base of a transistor MeT These transistors serve to trigger a bis-stable transistor circuit MeT MeT in response to the respective input signals, from which two output transistors MeT and MeT are alternately closed. By this arrangement an input signal from the upper matrix will close the transistor MeT so as to connect the common line with the INP network of the lower flip-flop system and vice versa.

More specifically the base of the transistor MeT is connected to a point in a voltage divider comprising resistors rm rm rm The line dc is connected to this divider between the resistors rm and rm A condenser 0M is shunted across the resistor rm so as to absorb faulty flash impulses or induced alternating current to thereby suppress any incidental shifting of the circuit. In the initial condition the transistor MeT is closed so that the potential on the emitter is determined by the voltage divider rm rm rm The voltage on the collector of the transistor MeT is hereby relatively positive and this potential is applied to the base of the transistor MeT through the rC-link rm Cm so that this transistor will be open. The same relatively positive voltage is applied to the base of the transistor MeT,- so that this transistor will be opened.

With the transistor MeT open the potential on its collector will be relatively negative and this potential is applied to the base of a transistor MeT through the resistance rm rm so as to keep this transistor closed. The various voltage dividers are so adapted that in the initial condition both the transistors MeT and MeT are closed. The collectors of the transistors MeT and MeT are connected to the inputs of the networks INP res-p. INP

while the emitters thereof both are connected to the common line y.

The data line dc is connected to the base of the transistor MeT through voltage dividers similar to those associated with the transistor MeT The positions of the transistors here describe-d correspond, as will be appreciated, with the transistor MeT opened and the transistor MeT closed to the schematic position of the switch shown in FIGURE 6 in full lines. The first fifteen data switches will cause sequential shifting of the upper flip-flop arrangement with desired actuation in sequence of the first three operation performing members H H H which, as shown, are connected to the distributor M which is associated with the upper flipfi-op arrangement.

When the matrix line number sixteen of the upper flipflop arrangement is rendered operative, the positive voltage on the line dc' is applied to the transistor MeT which is opened, whereby the transistor MeT is closed. Thereby the collector of the transistor MeT is rendered positive and causes the opening of the transistor MeT the collector of which thereby is rendered negative and closes the transistor MeT and opens the transistor MeT which corresponds to switching over the switch schematically shown in FIGURE 6 to the position shown in dotted lines, so as to connect the y-line through the transistor MeT to the input INP or the lower flip-flop arrangement.

By the change of the operating conditions of the MeO network here described the transistor MeT is not open, but remains closed until'the second set of fifteen data switches has caused sequential switching of the lower flipfiop arrangement with corresponding actuation of the operation performing members associated with the distribuj tor M' of the lower flip-flop arrangement.

When the matrix line number sixteen of the lower flipflop arrangement is selected and a positive voltage thereby is applied to the line dc this operates on the base of the transistor MeT whereby the latter transistor is opened, which again causes the closing of the transistor MeT whereby the transistor MeT is opened and the transistor MeT is opened, so as to repeat the cycle with the upper flip-flop arrangement.

It will be appreciated that by connecting two flip-flop arrangements in the simple manner shown in FIGURE 6, a series connection can be made which doubles the number of available data signal lines which are constituted by the matrix output lines.

It will be appreciated that an advantage of the apparatus according to the present invention is that it provides for fast shifting of the flip-flop counter device by means of data signals from the machine. It is thereby possible practically without any time delay during the complete machine cycle to plan the automation with a substantially increased number of data signal means on the machine compared with the number of operation performing members. With an 0.4 millisecond time constant of the IN]? network as hereinbefore mentioned it is rendered possible to process for example ten data signals in not substantially more than 4 milliseconds, which opens the possibility of adding to the machine equipment practically any desired number of data signal means which again provides for a faster operation cycle.

It may, therefore, in many cases be desired to have a substantial number of data signal lines available.

The binary counter control apparatus also provides for this possibility, and FIGURES 8 and 9 show with the gem eral circuit illustrated in FIGURE 9 a modification which enables multiplication of the number of available matrix output lines from two binary counter devices, i.e., a system in which the two groups of each fifteen available matrix lines from each of four flip-flops can be rendered effective as two-hundred and twenty-five data signal lines.

The system comprises an upper or first binary counter with its matrix which has a plurality of output lines to be made operative in sequence, and a lower or second binary counter with its appertaining matrix having a plurality of output lines to be made operative in sequence. The matrix system has a plurality of matrix groups of fifteen. Each group includes only one line of the first binary matrix and has all the lines of the second binary matrix available as input lines as well as output lines. In each group the single input line from the first or upper matrix is connected with all the fifteen input lines from the second or lower matrix. The output lines of the group are rendered operative in sequence because the single input line from the first group remains operative while the individual lines from the other groups are rendered effective in sequence. Furthermore, the groups are rendered operative in sequence by shifting the single input line of the groups, i.e., the line which belongs to the matrix of the first binary counter each time when the entire num ber of lines of each group, i.e., the output lines from the second binary counter of the preceding group have been shifted.

In FIGURE 9 the first four groups representing the data signal lines a 11 u u M31 4 and 14 u respectively, are shown with their complete connection with the two binary matrices. The remaining groups representing the data signal lines u n and up till u 11 are only shown with the connection of the two exterior lines of the respective groups.

In FIGURE 9 also the INP network is shown with its connection to the y-line as well as the two reset lines de' and de which represent the sixteen stage of each of the binary counters.

The connections with the inputs of the matrix system shown are illustrated by dots, the physical equivalents of which are gates or, as shown in FIGURE 8 DPuef works which render the output lines or data signal lines operative only when both matrix lines at a dot intersection are opera-tive.

As apparent from FIGURE 9, a matrix is provided with a first group il -H in which all the connections are between the first matrix output line um of the first binary system and all the matrix output lines um' um' um' of the second binary matrix.

In a similar way the next group of data signal lines u 11 has as input lines the second output line um of the first binary matrix and again all the output lines um um' um' of the second binary matrix.

This results in the matrix system shown in FIGURE 9 with a plurality of matrix groups each of which includes as an input one line from the first matrix of the first binary counter and a plurality, preferably all the lines of the second matrix of the second binary counter as input lines with a corresponding number of output lines. The dot connecting renders the output lines effective when both input lines are efifective. This means that in the matrix system shown, the output lines of each matrix group are rendered operable in sequence by the shifting of the second binary counter only. When the lines of one group have been used the next matrix group is rendered operable by the shifting of the first binary counter only one step. This shifting is controlled by the second binary counter when it has been through its complete cycle of shifting, i.e., when the sixteenth line de" of the second binary counter matrix is made operative.

In the embodiment shown in FIGURE 8, the matrix output lines in the upper flip-flop system are rendered operative by means of a positive voltage derived from the DP networks, while in the lower fiip-fiop system the matrix output lines are rendered operative with negative potential through inverted DP networks" referred to as DN networks. Each binary digit of the upper flip-flop system is retained during a complete digital cycle of the lower flip-flop system. The lower binary system is always switched stage-by-stage At the end of each completed cycle of the lower system it switches the upper system one stage which is retained while the lower system again runs through its cycle, etc.

More specifically, the apparatus shown in FIGURE 8 has a first plurality of control means D1 D1 D1 all of which are connected with the first matrix output line 24m of the upper flip-flop system, a second plurality of control means DI DI' DI' all of which are connected with the second matrix output line-11m of the upper flip-flop system, etc. These control means are individually connected with the output lines um' um' um' of the matrix of the lower flip-flop system. Furthermore, the control means has output lines in such a manner that the first plurality of control means DI D1 D1 individually are connected to a first plurality of output lines to be rendered operative as data signal lines and marked M I12, 14 r4 The second plurality of control means DI' DI' has in the same manner output lines to be rendered effective as data signal lines and referred to as u U17 11 etc.

The control means, i.e. the DI-means, includes means to render the output line which is connected with the respective control means effective when both of the matrix output lines from the upper flip-flop system as well as from the lower flip-flop system are rendered eifective. By way of example an output line which is connected with a DI-means which is connected to line number five of the upper matrix and line number eleven of the lower matrix will only be rendered effective when these two matrix output lines are effective simultaneously, which will be at the binary digit 1101 of the upper flip-flop system and binary digit 1010 of the lower flip-flop system, which corresponds to the line in question being numbered as data signal line 11 calculated in that way that the preceding number of total digits counted by both flip-flops is five times fifteen plus ten.

In the embodiment shown in FIGURE 8 the DI-means includes a transistor referred to as DIT with reference to the D1 control means. The emitters of the transistors in the first fifteen DI-means are all connected to the first matrix output line arm of the upper flip-flop system. The emitters of the transistors in the next fifteen DI-means DI' DI' are all connected to the second matrix output line um of the upper flip-flop system, etc.

The first fifteen data lines u r1 are individually 

1. IN AN AUTOMATION SYSTEM FOR A WORKING MACHINE HAVING A PLURALITY OF ELECTRICALLY CONTROLLED OPERATION PERFORMING MEMBERS ADAPTED TO BE CONTROLLED BY COMMAND SIGNALS TO PROVIDE SEQUENTIAL OPERATION OF SAID MEMBERS FOLLOWING A PREDETERMINED SEQUENCE IN COMBINATION: A BINARY COUNTER DEVICE, A PLURALITY OF DATA SIGNAL MEMBERS ON SAID WORKING MACHINE EFFECTIVELY PROVIDING DATA SIGNALS, MEANS OPERATIVELY CONNECTED WITH SAID BINARY COUNTER DEVICE AND OPERABLE TO SWITCH SAID BINARY COUNTER DEVICE EXCLUSIVELY BY SAID DATA SIGNALS, BINARY-TO-DECIMAL CONVERSION MEANS OPERATIVELY CONNECTED WITH SAID COUNTER DEVICE AND PROVIDING A PLURALITY OF SEQUENTIALLY ENERGIZABLE CIRCUIT MEANS SELECTIVELY RENDERED EFFECTIVE IN DECODED CORRELATION WITH THE BINARY DIGITS IN RESPONSE TO SWITCHING OF SAID BINARY DEVICE, AND MEANS OPERATIVELY CONNECTING SAID CIRCUIT MEANS WITH SAID OPERATION PERFORMING MEMBERS FOR DERIVING COMMAND SIGNALS FOR SAID OPERATION PERFORMING MEMBERS FROM SAID CIRCUIT MEANS. 